1. Field of the Invention
This invention relates generally to integrated circuits and to processes for manufacturing integrated circuits. More particularly, this invention relates to nonvolatile flash memory circuits fabricated with logic and linear circuits as a system-on-chip (SoC) and to processes for manufacturing nonvolatile flash memory circuits fabricated with logic and linear circuits as a system-on-chip (SoC).
2. Description of Related Art
As is known in the art, Flash nonvolatile memory is a solid-state memory technology that is widely used in many applications such as consumer cell phones and personal digital assistants to provide permanent data storage. The NAND Flash and NOR Flash memory have emerged as the dominant varieties of non-volatile semiconductor memories. The NAND Flash memory has a very small cell size and is used primarily as a high-density data storage medium. Alternately, the NOR Flash has approximately one quarter the density of the NAND flash memory and is typically used for program code storage and direct execution. The advantages of the NAND flash are higher memory density and thus lower bit cost, relatively fast write speed, and lower active power. The advantages of the NOR flash memory are relatively fast read speed and random access to provide ease of access for executing programming code.
NOR flash memory cells suffer from a punch-through phenomenon of the MOS charge retaining transistors for present advanced integrated circuit manufacturing technology nodes. Punch-through is caused when drain and source depletion regions merge, if a sufficiently large reverse bias is applied. This occurs with MOS transistors with very short channel lengths. The energy barrier that keeps the electrons in the source region of an NMOS transistor is lowered when the drain and source depletion merge. In this instance many electrons start to flow from the source to the drain even when the gate voltage is below the threshold voltage level of the NMOS transistor and the NMOS transistor is not supposed to conduct. This leakage current is sufficient large to cause the consumption of a relatively large amount of power during programming. The MOS charge retaining transistors are designed to have a channel length that is sufficiently large to prevent the punch-through.
The NAND flash memory cell is structured to have a serial NAND string with a gating transistor overcomes this scaling problem and is in mass production at the present advanced integrated circuit manufacturing technology minimum feature size of approximately 19 nm. However, NAND flash memory has a relatively slow read speed and is thus not suitable for an embedded application. While there are embedded NAND and NOR flash memory designs, there is no true embedded flash memory technology that is available for mass production in the semiconductor industry that has low power consumption to meet the requirement of “Green Memory”. Nonetheless, the demand for an integrated circuit process capable of having a NAND and NOR flash nonvolatile memory is increasing, because more and more System-on-Chip (SoC) integrated circuits are required with the embedded flash memory designs.